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does not allow OVD switching. The interface circuitry gets information on CL output validity and in turn informs the environment about CL readiness to input data processing. When an input data arrives CL changes its state to "transient", current consumption increases to 10-4-10-2A, which switches the OVD, thus informing the interface circuitry about output invalidity. The latter lets the environment know about CL business.
After the computations in the CL are finished, the current consumption decreases down to the steady state value, and the OVD sends a signal of output validity.
4.1 Information carrying signal
Current consumption by CMOS CL contains useful information on CL state. CMOS CL is a network of CMOS gates, so the current consumed by CL is a superposition of currents consumed by CMOS gates included in the CL. Each CMOS gate contains PMOS transistor and NMOS transistor networks (Fig.5). While a gate is in a steady state either the PMOS or the NMOS network is in a conducting mode. When a gate switches the non-conducting transistor network becomes conducting. There is usually a short period in switching time when both networks are in a conducting mode.
Generally, current consumed by a CMOS gate includes three components [9,10]:
(a) leakage current Ilk passing between power supply and ground due to finite resistance of non-conducting transistor network;
(b) short-circuit current Isc flowing while both networks are in a conducting mode;
(c) load capacitance CL charge current ILC flowing while a CMOS gate is switching from low to high output voltage via conducting PMOS network and CL .
SPICE simulation has shown  that amplitude of current consumed by a typical CMOS inverter depends on CL and is limited by the non-zero resistance of the conducting PMOS network (Fig.7). The integral of consumed current is proportional to CL . When a gate switches from high to low output voltage, the component ILC is negative by direction and negligible by value (Fig.7b). It is evident, the switchings from high to low output voltage occur at the expense of energy accumulated in CL during the previous switching from low to high output voltage. The component Isc does not depend on direction in which a gate switches.
The component ILC equals to ILC = CL*Vdd *f where Vdd is a power supply voltage, f is a gate switching frequency. Veendrick has investigated the component Isc dependencies on CL and rise-fall time of input potential signal . He showed that if both input and output signal have the same rise-fall time, the component Isc cannot be more than 20 percent of summary current consumption . However, when the output signal rise-fall time is less than input one, the component Isc can be of the same order of magnitude as ILC. In that case it must be taken into account. As to the component Ilk, it entirely depends on CMOS process parameters and for state of the art CMOS devices Ilk is about 10-15 -10-12 A.
So, the analysis of CMOS gate current consumption allows us to conclude that in transient state a CMOS gate consumes a current I*= Ilk+Isc+ILC and in steady state it consumes only Ilk